An investigation into the role of LET and supply voltage in determining the critical charge for Single Event Upset in a 65-nm CMOS SRAM

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عنوان دوره: اولین دوره بین المللی و بیست و هشتمین دوره ملی (1400)
Continuous downscaling of CMOS technology results in a decrease in minimum charge (Qcritical) upsetting the logic state of a memory cell which are mainly attributed to the lower supply voltage. In this paper, the Qcritical required to cause upset in a 6T SRAM cell designed in 65-nm process is investigated in three different supply voltages. To this purpose, a memory cell was designed using the Mixed-Mode and Victory modules of Silvaco TCAD tool. Then, the variations in output voltages were studied after striking charged particles with different values of Linear Energy Transfer (LET). The Qcritical was obtained by integrating the output current when the output voltages were inverted. The results showed that lowering in supply voltages has been led to a decrease in Qcritical.
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